Resources
Documents
PEMS I, II, III
Change

1Gbit – 8Gbit QED Dual-Quad SPI P-SRAM Memory

Receive Updates to this Datasheet

Optional: Enter your email address to be notified when this datasheet is updated.

Revision G.3 - July 15, 2024

Latest Revision Changes

Updated Power UP Behavior to allow for Vcc and Vccio mismatch
Sign up for our quarterly newsletter.
Avalanche Technology Inc.
3450 West Warren Avenue,
Fremont, CA 94538
(510) 897-3300
info@avalanche-technology.com
©2024 Avalanche Technology | All Rights Reserved | Privacy Policy