Avalanche Adds Two New Small, Low Power Gen 3 MRAM Devices, Ideal for Efficiently Booting Lightweight SoCs & FPGAs
Fremont, CA, August 26, 2024 – Avalanche Technology, the leader in next generation MRAM technology, announced today the rollout of two new additions to the leading Aerospace & Defense Gen 3 STT-MRAM product suite: 64Mb and 128Mb densities. For space-targeted processors and FPGAs with modest configuration image requirements, these new products offer improved reliability, size and power for booting vs traditional legacy Flash-based methods.
Responding to a groundswell of industry demand, Gen 3 STT-MRM is recognized as the vastly superior replacement to Flash memory, whose radiation susceptibility creates reliability risks and inordinate hardware & software complexity.
Avalanche’s newest Gen 3 STT-MRAM products offer the suite’s optimized radiation resilience and high reliability. Additionally, these compact (10x10mm FBGA), low power (15mA active) low density devices are electrically pin-compatible with existing high density Gen 3 DQSPI devices, providing full scalability of density from 64Mb to 8Gb with the same pinout.
Available in the Space Grade family and the recently introduced enhanced Space Grade-E family, the latest products will have pin-compatible platform support for varying mission requirements for density, qualification and screening. Avalanche will work with industry partners to ensure that extension of NASA PEMS and QML flows is supported, as with the remainder of the Gen 3 portfolio. Additionally, die-level options exist for multichip modules, enabling FPGA, SoC and ASIC designers an opportunity to boost SWaP and reliability. These devices and their development kits are available now, orderable through regional distribution partners.
“As we continue to innovate with high-reliability rad-hard and rad-tolerant semiconductor solutions, we are always searching for new methods to improve SWaP and reliability for the Aerospace and Defense community,” said Patrice Parris, Chief Technology Officer at VORAGO Technologies. “By leveraging Avalanche’s idealized boot solutions, now available with a size and density profile that matches the needs of our rad-hard and rad-tolerant MCUs and MPUs, we can accomplish both goals for a highly optimized processing solution.”
“By further extending our portfolio of idealized boot solutions for space, we’re answering the call for improved SWaP and reliability across the continuum of processor & FPGA types”, said Danny Sabour, VP of Sales & Marketing at Avalanche Technology. “While maintaining pin compatible scalability and robust write protection schemes, we continue to enable software-defined hardware platforms and in situ multi-mission adaptability.”
Avalanche Gen 3 Space Grade and Space Grade-E MRAM
Gen 3 Space Grade and now Space Grade-E are offered as standard products in Parallel with asynchronous SRAM-compatible timing and Dual QSPI high speed serial interface in various pin compatible density options from 1Gb to 8Gb.
Designed for High-Reliability with multibit error correction and industry leading 1016 write cycle endurance, data is always non-volatile.
The devices come in a small footprint packaging (RoHS-compliant and leaded) and extended operating temperature range (-40°C to 125°C) with JEDEC qualification. There are additional qualification screening and packaging options available through partners. More information about Avalanche’s MRAM-based Persistent SRAM (P-SRAM) products is available at https://www.avalanche-technology.com/products/discrete-mram/space/.
About Avalanche Technology
Avalanche Technology is the space technology leader enabling the Orbital Internet. With a proven STT-MRAM portfolio at multiple geometry nodes combined with an intellectual property portfolio of over 300 patents and applications, Avalanche is the only provider of scalable unified memory architecture for industrial, IoT, aerospace and storage applications that are Space-tested and proven. Avalanche’s Perpendicular STT-MRAM technology is the frontrunner to replace traditional Flash and SRAM for unified memory architectures in future SOC systems, delivering high performance and low power with a path to continued scalability. Learn more at avalanche-technology.com. More perspectives from Avalanche include:
